Slave Select (SS):

• Master selects a slave by pulling SS low (active-low signal).
• High = not selected, Low = selected.

Wait Period:

• If needed (e.g. ADC conversion), master waits before sending clock pulses.

Data Transfer (Full-Duplex):

• Each clock cycle transmits one bit in both directions:
  • Master → Slave on MOSI
  • Slave → Master on MISO
• Even if communication is one-way, both shift registers still shift.

Shift Registers:

• Master and slave each have a shift register (commonly 8-bit, but can be 12/16-bit).
• Data is usually sent MSB-first (but can be LSB-first if configured).
• On each clock edge:
  1. Both devices shift out one bit.
  2. On the next edge, each samples the incoming bit.
• After all bits are clocked, registers are fully exchanged.

Continuing Transmission:

• Shift registers can be reloaded for more data.
• When done, master stops clocking and usually deselects the slave.

Multiple Slaves:

• Single slave: SS can be tied permanently low if allowed.
• Multiple slaves:
  • Multidrop: Each slave gets its own SS line.
  • Daisy-chain: Only one SS line is needed.

Inactive Slaves:

• Ignore clock and MOSI when not selected.
• MISO must be tristated (High Impedance State) to avoid bus contention (use tristate buffers if needed).